A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph relies at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point development of a multi-core computing device with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache dependent sequentially constant shared reminiscence. This opens the best way to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the improvement of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.

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Proof. By contradiction. Assume a path s[0 : k] with k > #G exists in the circuit. All si are gates except possibly s0 which might be an input. Thus, a gate must be (at least) twice on the path: ∃i, j : i < j ∧ si = sj . Then s[i : j] is a cycle3 . 3 This proof uses the so called pigeonhole principle. If k + 1 pigeons are sitting in k holes, then one hole must have at least two pigeons. 2 Some Basic Circuits 33 Since every path in a circuit has finite length, one can define for each signal s the depth d(s) of s as the number of gates on a longest path from an input to s: d(s) = max{m | ∃ path s[0 : m] : s0 ∈ In ∧ sm = s} .

2 Some Basic Circuits a a n n ∨ n-Zero 1 zero 37 nzero 1 nzero zero (a) symbol (b) implementation Fig. 12. n-bit zero tester a a b b n n n n n n-eq 1 n-Zero 1 eq neq 1 eq (a) symbol 1 neq (b) implementation Fig. 13. n-bit equality tester The inputs a[n − 1 : 0], b[n − 1 : 0] and outputs eq, neq of an n-bit equality tester in Fig. 13 satisfy eq ≡ a = b , neq ≡ a = b . The implementation uses neq(a[n − 1 : 0]) = nzero(a[n − 1 : 0] ⊕ b[n − 1 : 0]) , eq = neq . An n-decoder is a circuit with inputs x[n − 1 : 0] and outputs y[2n − 1 : 0] satisfying ∀i : yi = 1 ↔ x = i .

This includes the classical definition of the depth d(g) of a gate g in a circuit as the length of a longest path from an input of the circuit to the gate. For the purpose of timing analysis in a later section, we also introduce the function sp(g) measuring the length of a shortest path from an input of the circuit to gate g. We present the classical proof by pigeon hole principle that the depth of gates is well defined. By induction on the depth of gates we then conclude the classical result that the semantics of switching circuits is well defined.

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