By Himanshu Bhatnagar
Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment variation describes the complicated suggestions and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. additionally, the whole ASIC layout move method particular for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time program of Synopsys instruments, used to strive against quite a few difficulties obvious at VDSM geometries. Readers might be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties with regards to each one part of the layout movement are pointed out, with strategies and work-around defined intimately. moreover, an important concerns on the topic of structure, including clock tree synthesis and back-end integration (links to format) also are mentioned at size. additionally, the publication includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, exact in the direction of optimum synthesis answer. goal audiences for this publication are working towards ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT thoughts.
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Extra info for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
At this stage an additional step is necessary to complete the clock tree insertion. As mentioned above, the layout tool inserted the clock tree in the design after the placement of cells. Therefore, the original netlist that was generated from DC (and fed to the layout tool), lacks the clock tree information (essentially the whole clock tree network, including buffers and nets). Therefore, the clock tree must be re-inserted in the original netlist and formally verified. Some layout tools provide direct interface to DC to perform this step.
Various methods of transferring the clock tree information to the design are explored in detail in Chapter 9. For the sake of simplicity, let us assume that the clock tree information is present in the tap_controller design. The design is now ready for routing. In a broad sense, routing is performed in two phases – global route and detailed route. During global route, the router divides the layout surface into separate regions and performs a point-to-point “loose” routing without actually placing the geometric wires.
This operation is ASIC DESIGN METHODOLOGY 11 usually performed a number of times until the timing requirements are satisfied. 6 Placement, Routing and Verification As the name suggests, the layout tool performs the placement and routing. There are a number of methods in which this step could be performed. However, only issues related to synthesis are discussed in this section. The quality of floorplan and placement is more critical than the actual routing. Optimal cell placement location, not only speeds up the final routing, but also produces superior results in terms of timing and reduced congestion.