By Steven Carroll, Walden Ko, Mark Yankelevsky (auth.), Henry G. Dietz (eds.)
This e-book constitutes the completely refereed post-proceedings of the 14th overseas Workshop on Languages and Compilers for Parallel Computing, LCPC 2001, held in Lexington, KY, united states, in August 1-3, 2001.
The 28 revised complete papers offered have been rigorously chosen in the course of rounds of reviewing and development. All present matters in parallel processing are addressed, specifically compiler optimization, HP Java programming, power-aware parallel architectures, excessive functionality purposes, energy administration of cellular pcs, info distribution, shared reminiscence structures, load balancing, rubbish assortment, parallel elements, task scheduling, dynamic parallelization, cache optimization, specification, and dataflow research.
Read or Download Languages and Compilers for Parallel Computing: 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1–3, 2001 Revised Papers PDF
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Extra info for Languages and Compilers for Parallel Computing: 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1–3, 2001 Revised Papers
Code, but they are not mandatory. Instead, multi-rate semantics can be attached to other syntactical SILAG. constructs, such as conditional expressions and loops. 6), in order to perform rate control transformations manually. 3 DSP target architectures Many aspects of architecture synthesis are specific to the architectural style envisioned. AL-II target architecture in particular will be described. The physical details of the architecture will be abstracted up to the level the synthesis programs are working on.
L-n, the designer allocate, the type, that can be used by the compiler. Depending on the arithmetic complexity of the algorithm, the frame rate, the maximal chip area, the total power dissipation and on special constraints concerning I/O, the designer takes into account the module siles, the power dissipation, the versatility and the execution speed of the individual operators. 4. BUILDING A DSP SILICON COMPILER 45 factors. Memor;y management For descriptions with multidimensional data streams, efficient organiltJtion of the memory is crucial for the final design efficiency.
For instance, a delay line can be implemented in dual-port registers, in a FIFO or in a single-port RAM. The compiler is responsible for allocating and organising the memory efficiently, based on the lifetimes of all signal values. This can be done at compile time (see chapter 3). 5 Operations Signals are transformed by applying operations. Operations are represented by function call.. GII description must contain one main function. , no user-supplied definition is required. GII offers a number of primitive functions, such as the delay operator, particularly suited for describing DSP systems.